Politecnico di Torino | Servizi per la didattica

KEYWORD

Keyword: EMBEDDED SYSTEMS

TESI ALL'ESTERO Adaptive deep learning workload for nanorobotic System-on-Chip JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

TESI ALL'ESTERO Advanced C++14 Multithreading Modelling of Electronics Systems SANCHEZ SANCHEZ EDGAR ERNESTO SAVINO ALESSANDRO TESTGROUP - TESTGROUP

TESI AZIENDA Advanced control logic for traction electric machines VIOLANTE MASSIMO DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD

Approximate Computing Benchmarks for Embedded Systems SAVINO ALESSANDRO TESTGROUP - TESTGROUP

Binary Code Compression & Decompression via custom Executable Packers PRINETTO PAOLO ERNESTO GR-21 - TESTGROUP - TESTGROUP

TESI AZIENDA Boot Time Estimation Model & Tool TORCHIANO MARCO SOFTWARE ENGINEERING GROUP - SOFTENG

Convolutional Neural Network cores towards Deep Space STERPONE LUCA GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD

TESI AZIENDA Deep Learning Compiler for Smart Sensors JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Deep Learning compiler for ultra-low-power multi-core platforms based on RISC-V JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

TESI ALL'ESTERO Deep Learning on Ultra-low-power Autonomous Flying Nano-drones JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Deep learning for biometric identification using PPG signals JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

TESI AZIENDA Design of a C++ control application for innovative laser-based tires profiling system @Tire Profiles Italy PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Design of a FPGA-based MPEG compression algorithm for UAV payload DI CARLO STEFANO PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Design of a FPGA-based OCR algorithm for UAV payload control DI CARLO STEFANO PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Design of a FPGA-based TPM Security Device DI CARLO STEFANO PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Design of a FPGA-based processor for UAV payload control DI CARLO STEFANO PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Design of a secure challenge-response protocol based on Physical Unclonable Functions (PUFs) for ARM platforms PRINETTO PAOLO ERNESTO GR-21 - TESTGROUP - TESTGROUP

Development and comparison of convolutional layers implementations for deep neural networks on microcontrollers. JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Development fo an open source test system for lab characterization of nanostructured materials and surfaces JANNER DAVIDE LUCA AA - Glasses, Ceramics and Composites

Development of a QEMU-based environment for the reliability characterization of Xilinx on-chip systems BERNARDI PAOLO GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD

Development of a Security-Oriented RISC-V SoC Architecture PRINETTO PAOLO ERNESTO GR-21 - TESTGROUP - TESTGROUP

Development of an innovative Hybrid HW/SW Architecture DI CARLO STEFANO PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Effective and secure challenge-response protocol for FPGA-based PUFs (Physical Unclonable Functions) PRINETTO PAOLO ERNESTO GR-21 - TESTGROUP - TESTGROUP

Efficiency-driven optimization of deep neural network architectures JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Embedded Systems Security via Control-Flow Integrity PRINETTO PAOLO ERNESTO GR-21 - TESTGROUP - TESTGROUP

Enhancing dependability in FPGA-based systems for future space exploration missions DI CARLO STEFANO PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Experimental evaluation of High Level Synthesis Tools and related Design Styles definition DI CARLO STEFANO PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Experimental evaluation of real-time protocol stacks CIBRARIO BERTOLOTTI IVAN IEIIT/CNR COMPUTER ENGINEERING AND NETWORKS GROUP

FPGA-based accelerators for future Mars exploration missions DI CARLO STEFANO PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

FPGA-based implementation of Cryptographic Algorithms for the Advanced Open-source Security Platform SEcube™ PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Fast and Secure Image Processing applications PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Hardware-Based Schedulers approaches for Linux OS REBAUDENGO MAURIZIO SAVINO ALESSANDRO ELECTRONIC CAD & RELIABILITY GROUP - CAD TESTGROUP - TESTGROUP

Implementation of Reduced-Precision Convolutional Neural Networks JAHIER PAGLIARI DANIELE PONCINO MASSIMO GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Integrating convolutional neural networks accelerators in commercial MCUs JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

TESI ALL'ESTERO Integration of Deep-learning-powered Drone-to-drone Pose Estimation on Ultra-low-power Autonomous Flying Nano-drones JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Internet Protocol (IP) support for SEcube™ board PRINETTO PAOLO ERNESTO GR-21 - TESTGROUP - TESTGROUP

Memory access optimizations for executing deep neural networks on multi-core microcontrollers JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Multithreaded support Embedded Application on RISC-V SANCHEZ SANCHEZ EDGAR ERNESTO SAVINO ALESSANDRO ELECTRONIC CAD & RELIABILITY GROUP - CAD TESTGROUP - TESTGROUP

Optimization of Transformer Deep Neural Networks on Multi-Core MCUs JAHIER PAGLIARI DANIELE DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA ELECTRONIC DESIGN AUTOMATION - EDA GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Secure Data Management in e-Health Applications through the Advanced Open-source Security Platform SEcube™ PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Secure Device Drivers Development for the Advanced Open-Source Security Platform SEcube™ PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Secure Edge-Computing exploiting Artificial Intelligence Applications PRINETTO PAOLO ERNESTO GR-21 - TESTGROUP - TESTGROUP

Secure File System Development for the Advanced Open-source Security Platform SEcube™ PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Secure Internet-of-Things (IoT) applications in Industry 4.0 PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Securing IoT Communications via the SEcube™ Platform PRINETTO PAOLO ERNESTO GR-21 - TESTGROUP - TESTGROUP

Software Development Kit (SDK) Development for the Advanced Open-source Security Platform SEcube™ PRINETTO PAOLO ERNESTO TESTGROUP - TESTGROUP

Study and development of a Reconfigurable-based Adaptive Artifical Intelligence Core STERPONE LUCA GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD

Study and redesign of the user interface for controlling audio visual systems in the classroom CORNO FULVIO DE RUSSIS LUIGI DAUIN - GR-10 - Intelligent and Interactive Systems - e-LITE

Sviluppo di algoritmi di monitoraggio su sistemi Embedded con architerttura ARM per applicazioni ferroviarie. BOSSO NICOLA Laboratorio di costruzione e dinamica ferroviaria

SystemC-AMS extensions to improve the design of modern systems VINCO SARA DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA