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Keyword: RISC-V

An evolutionary-based environment to generate stress programs for a RISC-V processor  SONZA REORDA MATTEO  DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Automated Synthesis of Vulnerable RISC-V based Architectures  PRINETTO PAOLO ERNESTO  GR-21 - TESTGROUP - TESTGROUP
Binary Code Compression & Decompression via custom Executable Packers  PRINETTO PAOLO ERNESTO  GR-21 - TESTGROUP - TESTGROUP
Evaluation methods for the robustness of a radiation tolerant RISC-V processor for deep space applications  STERPONE LUCA  DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
azienda TESI AZIENDA esteroTESI ALL'ESTERO Green-Five: An open-source system-level power analysis method for energy efficient RISC-V ISA  RIENTE FABRIZIO  EC à IMT Atlantique/Lab-STICC, Brest, France.  VLSI THEORY, DESIGN AND APPLICATIONS (VLSILAB)
RISC-V for automotive  BURRELLO ALESSIO  JAHIER PAGLIARI DANIELE  PONCINO MASSIMO  VINCO SARA  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Simulation of power flows in a RISC-V based system  JAHIER PAGLIARI DANIELE  PONCINO MASSIMO  VINCO SARA  DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Studio e sviluppo di nuove architetture per applicazioni aerospaziali basate sul processore RISC-V  STERPONE LUCA  DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
Study and development of Reliable RISC-V Architectures for space applications  DE SIO CORRADO  STERPONE LUCA  ASAC Lab - Aerospace, Safety, and Computing Lab  DAUIN - GR-05 - ELECTRONIC CAD and RELIABILITY GROUP - CAD