Design of a SPMI Slave Interface IP for Power Management IC
Thesis in external company
Reference persons DANIELE JAHIER PAGLIARI
External reference persons Marco Castellano (ST Microelectronics)
Thesis type EXPERIMENTAL, HARDWARE, HARDWARE DESIGN, SIMULATIVE AND EXPERIMENTAL
Description The main goals of the thesis are to understand the SPMI protocol and to implement a fully compliant SPMI slave IP. All the steps of the Front-End flow are followed, starting from the analysis of the specifications, going through RTL description (preferably using Verilog), and verification, and ending with the implementation, by defining constraints and performing the synthesis. The SPMI protocol is meant to be used especially for mobile application for transferring data about power and state of several driving IC in a phone or laptop, at a high speed rate (up to 26 MHz). The interface with the other IPs in the SoC is another crucial point to deal with. As a SPMI slave, a Master interface for the internal system must be designed, following the AMBA protocol.
Interested candidates must send an email to firstname.lastname@example.org attaching their CV and exams' transcript with scores.
Required skills Digital Design basics. VHDL or Verilog language
Notes Thesis in collaboration with a R&D group of ST Microelectronics, located in the Milan area. The work can be carried out partially remotely, and economic compensation is foreseen.
Deadline 31/01/2023 PROPONI LA TUA CANDIDATURA