PORTALE DELLA DIDATTICA

Ricerca CERCA
  KEYWORD

Development of a Soft Error tolerant Parallel Hash Table on FPGAs for safety critical applications

Parole chiave FAULT TOLERANCE, FPGA, FPGA ACCELERATION

Riferimenti LUCA STERPONE

Gruppi di ricerca DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD

Tipo tesi RESEARCH / EXPERIMENTAL

Descrizione A key component in Artificial Intelligence and Machine Learning applications is the fast execution of quicl search and retrieval of data. Hash tables are a fundamental data structure to perform these operation efficiently. In safety critical applications such as automotive or aerospace, it is not sufficient to have a performant architecture but it is also necessary to guarantee a given level of robustness and protection versus soft errors. In the present thesis, the student will explore, study and development a new architecture for implementing parallel and fault tolerant hash table for SRAM-based FPGAs for aerospace applications. The thesis will be performed in collaboration with the European Space Agency (ESA) and in cooperation with AMD/Xilinx.

Conoscenze richieste Design of Circuits and Systems in VHDL or Verilog.
Preliminary basic knowledge of FPGA architectures.


Scadenza validita proposta 10/09/2022      PROPONI LA TUA CANDIDATURA




© Politecnico di Torino
Corso Duca degli Abruzzi, 24 - 10129 Torino, ITALY
Contatti