Automated SystemC test environment generation from tables and natural language specification
Thesis in external company
keywords FUNCTIONAL VERIFICATION, NATURAL LANGUAGE PROCESSING, SYSTEMC
Reference persons LUCIANO LAVAGNO
External reference persons The thesis will be done at Punch, Torino.
Research Groups Microelectronics
Thesis type THEORY AND PROJECT
Description Modeling of embedded systems design includes various abstraction levels and corresponding methods for synthesis and verification. The manual translation of specifications into a formal implementation is a time-consuming and error-prone process.
To automate the generation of a test environment for SystemC components, a structured methodology must be implemented: it involves the definition and adoption of a test specification format that can be parsed by an algorithm able to generate the actual SystemC code.
The first phase of the thesis consists of automatic generation of the SystemC code for the test and validation of the module, from specifications written in a standard table format (Textual Normal Form) that describes the sequence of testing steps.
If time allows, the second phase is a stepwise transformation from semi-structured English text into Textual Normal Form using natural Language Processing methods.
Required skills SystemC modeling
Unified Verification Methodology
Notes Some knowledge of Machine Learning is a plus for the second phase.
Deadline 09/05/2023 PROPONI LA TUA CANDIDATURA