| KEYWORD |
RISC-V Core supporting protected code execution for low-power embedded consumer systems
Thesis in external company
Reference persons GUIDO MASERA
Research Groups VLSILAB (VLSI theory, design and applications)
Description Goal of the Thesis :
More and more customers require some level of customization to better fit their application in terms of data processing or data transfer, once the silicon is on the market.
The idea is to give to the customer the possibility to write their own code to be execute “safely” by the embedded microcontroller.
The goal of the thesis is understanding how to create a space for customers to load their custom code while the embedded CORE is running proprietary FW.
The challenges to solve:
a) IP protection: proprietary code should be protected so that it is impossible for the customer-code to maliciously readback our binary.
b) Protected Execution: how do we protect the execution of proprietary code? For example if the customer creates a while (1) {} in his code how do we guarantee our code is still executed when required?
c) Protected memory : make sure the customer code does not have access to reserved ram space (stack/heap) and also provide an architecture to exchange data in a controlled way between the two domain.
d) Development Environment: how do we offer a stable and easy to use environment so that customers can develop and compile easily, without much support?
The student will have to possibility to :
- Research among available RISC-V cores within and outside ADI, the most suitable one for our goal;
- Evaluate HW modification of the core currently in use within ADI and in case do all the RTL modifications;
- Integrates needed peripherals (Serial Interfaces like I2C or SPI, Timers, WDOG) if necessary;
- Work with State-of-the-Art tool for verification and implementation;
- Implement the CORE + peripherals on FPGA platform;
- Write necessary C code to prove functionality;
Required skills Candidates Requirements
- Digital Design and embedded system knowledge
- Good Knowledge of RTL language : VHDL and/or Verilog
- Proactivity and attitude to work in an international team
- Flexibility to work on different tasks
Notes Thesis work proposed by Analog Devices S.R.L. Milano, Italy
There is a salary for the duration of the thesis.
Interested students should send me a detailed CV.
Deadline 05/04/2024
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