| KEYWORD |
In Memory Computation tecniques applied to high-performance mathematical accelerator
Thesis in external company
keywords IN-MEMORY COMPUTING, MATHEMATICAL ACCELERATOR
Reference persons LUCIANO LAVAGNO, MIHAI TEODOR LAZARESCU
Description Starting from the implementation of an existing math accelerator, the thesis work consists in performing an architectural analysis in order to increase its computational capabilities using In-Memory Computing (IMC) techniques. The architectural analysis will be followed by the implementation, verification and synthesis phases.
Required skills - Good knowledge of hardware description languages (VHDL, Verilog), their usage and simulation.
- Basic knowledge of hardware verification languages (System Verilog, UVM) and functional and formal verification techniques.
- Basic knowledge of the silicon backend process (constraints, synthesis, place & route).
Deadline 30/05/2024
PROPONI LA TUA CANDIDATURA