| KEYWORD |
Development of a framework for the automatic generation of test oriented to verify the share memory access in a RISC-V based multicore system
keywords MEMORY CONSISTENCY ALGORITHMS, MICROPROCESSOR VERIFICATION, SOC VERIFICATION
Reference persons ANNACHIARA RUOSPO, EDGAR ERNESTO SANCHEZ SANCHEZ
External reference persons Andrea Parri, RIVOS Inc.
Research Groups DAUIN - GR-05 - ELECTRONIC CAD and RELIABILITY GROUP - CAD
Description To develop a framework to generate, run, and analyze directed, self-checking tests to verify compliance of the core(s) to the memory-ordering rules described in the RISC-V Unprivileged specification Manual. This project will focus on the pre-silicon verification of the selected cores/systems. Some tooling and literature exist for post-silicon/full-system verification of memory consistency. An initial part of the project will entail reviewing such literature. Later work may include adding "randomization" to the test set / generator as well as integration or comparison with other instruction sequence generators.
Required skills The ideal candidate(s) should have experience with RTL simulation and with the RISC-V ISA, but previous work with memory consistency models/verification is not required.
Deadline 13/10/2024
PROPONI LA TUA CANDIDATURA