| KEYWORD |
Power Island based DSP core for ultra-LP designs
Thesis in external company
Reference persons MARIO ROBERTO CASU
Research Groups VLSILAB (VLSI theory, design and applications)
Description ultra-low-power portable systems with DSP cores require a low IDDQ current in idle or stand-by mode and adaptive voltage scaling techniques to reduce dynamic power.
Objectives: the idea a partial re-design of an existing IVM core with the objective to split it in 2 or more power islands accordingly to the functional modes, each powered by an independent supply Implement predictive and systematic techniques in Verilog/C++ that dynamically adjust frequency and supply voltage enabling dynamic and leakage power optimization.
Activity Description: (1st thesis) front-end modification of the actual core (RTL and simulations), (2nd thesis) back-end flow with power islands. Dynamic and leakage power comparison between original and modified architecture.
See also inventvm semiconductor thesis opportunities october 2023.pdf
Required skills Verilog or VHDL, Matlab, FPGA design.
Deadline 01/12/2024
PROPONI LA TUA CANDIDATURA