KEYWORD |
High-performance network systems on reconfigurable hardware (FPGA)
keywords COMPANY, FPGA, HDL, VERILOG, VHDL
Reference persons CORRADO DE SIO, LUCA STERPONE
External reference persons LINKS Foundation contacts:
Alberto Scionti
Paolo Savio
Research Groups ASAC Lab - Aerospace, Safety, and Computing Lab, DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Thesis type COLLABORATION WITH A COMPANY
Description High-speed, low-latency networks are becoming a fundamental building block in many application contexts. For instance, in modern datacenters, high-speed, low-latency networks are required to better serving large AI models and big-data applications. FPGAs evolved in the past years to include more and more functionalities, like hardened processors and network building blocks. As such, modern FPGAs can be used to implement custom high-speed network interfaces (NICs).
The purpose of this thesis is the design and integration of custom a logic into an open source high-speed, low-latency NIC (Corundum). Specifically, the candidate will study the architecture of the open-source NIC, in order to design and integrate some custom logic (which can vary from simple HDL functions to RISC-V based cores) to perform packet processing at line-rate. The resulting designed network fabric will be able to perform routing of packets over a mesh-based network (bypassing the operating system), as well as providing hardware acceleration for the application level (e.g., address-based packet filtering). Validation experiments will be done at LINKS Foundation where a cluster of 6 FPGA boards is available.
Required skills Required Knowledge
- HDL (Verilog and/or VHDL) developing
The knowledge of Know high-level synthesis and other programming languages (C/C++, Python) is appreciated
Notes This thesis is developed in collaboration with Links Foundation
Deadline 08/01/2026
PROPONI LA TUA CANDIDATURA