KEYWORD |
Study and development of Reliable RISC-V Architectures for space applications
keywords FPGA, RELIABILITY, RISC-V, VHDL
Reference persons CORRADO DE SIO, LUCA STERPONE
External reference persons Giorgio Cora
Research Groups ASAC Lab - Aerospace, Safety, and Computing Lab, DAUIN - GR-05 - ELECTRONIC CAD and RELIABILITY GROUP - CAD
Description The objective of this thesis is to develop a custom RISC-V architecture designed in VHDL and implementable on Field-Programmable Gate Arrays (FPGA), targeting space applications. The primary goal is to modify a RISC-V core to provide support for an extended Instruction Set Architecture (ISA), enabling the development of an efficient on-demand testing protocol. This system aims to enhance the reliability of the architecture by enabling robust error detection capabilities and ensuring the continuity of operations in safety-critical environments.
The candidate will have access to state-of-the-art AMD FPGA platforms to implement and validate the proposed solution, ensuring its effectiveness and performance in real-case scenarios.
Required skills HDL
Programming
Deadline 13/01/2026
PROPONI LA TUA CANDIDATURA