Ricerca CERCA

Macromodels of High-Speed Interfaces



External reference persons Gianni Signorini, Intel Corporation - Munich, Germany

Research Groups EMC Group (Electromagnetic Compatibility)

Description The high-level of integration in modern Printed-Circuit- Boards (PCB), Packages and Dies, combined with the inevitable presence of parasitic resistive, inductive and capacitive components, can often lead to a degradation of signal quality; “Signal Integrity” simulations are aimed at studying the impact of interconnection non-idealities on communication reliability (electrical levels, signal distortions, Bit-Error-Rate (BER), etc.).
Macromodel-based simulations are the only viable approach to deal with the complexity of such analyses: transmitter and receiver circuits (I/Os), usually described by detailed transistor-level netlists, are substituted with accurate, efficient and equivalent representations; simulations run much faster, accuracy is guaranteed and verification coverage can be extended.
However, I/O macromodeling has become more and more a challenging task: the increasing speed (up to 10Gbps) and the reduction of signal amplitudes require outstanding model accuracy; furthermore, transmitters and receivers have been equipped with equalizers and other specialized circuit blocks that intentionally distort the signals in order to compensate the detrimental effects introduced by the interconnection non-idealities.

The candidate will learn and apply state-of-the-art modeling techniques for the macromodeling of I/O circuits. The focus will be put on IBIS models and Mpilog models.
IBIS (I/O Buffer Information Specification) is a de-facto standard for I/O circuit modeling; IBIS specification is developed and supported by the major consumer electronics manufacturers. IBIS-AMI (Algorithmic Modelling Interface) is an IBIS extension that is able to macromodel also equalizers blocks.
Mpilog is a very promising, innovative and alternative macromodeling approach to IBIS; Mpilog is a macromodeling framework developed by Politecnico di Torino in collaboration with IBM first, and later with Intel Corporation. The candidate will perform comparative analysis between IBIS and Mpilog models, working on real transmitter and receiver circuits for mobile electronics, implemented in leading-edge FinFET technologies. Afterwards, the candidate will contribute to enhance the Mpilog model structure to reproduce the effects of equalizers circuits; the work will be carried out in direct collaboration with the Mpilog development team at Politecnico di Torino and Intel Corporation.

See also  macromodels_msc_proposal.pdf 

Required skills The candidate should have some background in Electronics, Circuit Theory and Electromagnetics. Good programming skills (Matlab) are required. Proficiency with Circuit Simulation techniques (SPICE) and math are preferred. Part of this activity is configured as “research work”: personal commitment and creativity in finding solutions to problems are welcome. Being the work developed in collaboration with an international company, proficiency in English is required.

Notes See attachment

Deadline 30/09/2019      PROPONI LA TUA CANDIDATURA

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