Design of a configurable LLVM back-end for heterogeneous embedded platforms.
External reference persons Gianvito Urgese, Francesco Barchi
Research Groups ELECTRONIC DESIGN AUTOMATION - EDA
Thesis type EXPERIMENTAL
Description Many heterogeneous devices are currently available on the market; two of the most representative are Xilinx Zynq e Nvidia Jetson TX1. Usually these devices embed hardware (HW) accelerators capable to enable, for the execution of particular tasks, high computational power and low power consumption. In theory and on paper these devices are able to provide high performances as long as the application developers are able to exploit the HW-specific features during the programming phase.
In this context, we propose the thesis topic. The candidate is required to study and design a configurable LLVM back-end capable to compile generic software for a heterogeneous HW platform.
In the first phase of the thesis work, the candidate will study state-of-the-art compiling technologies, automatic parallelisation techniques, and several intermediate representation languages like LLVM-IR.
In the second step, the candida will try to use tools capable to identify pieces of code potentially parallelisable (kernels). Then, it will be developed a compiling back-end able to adapt and place the isolated kernels to the most likely HW available on the target architecture.
This back-end, during the kernel mapping/execution, should consider the compiling parameters defined by the user. Thus, the performances can be reduced to match the low power requirements, or vice-versa the best performances can be achieved to the detriment of the power saving.
Required skills • Good programming skill [Python, C, C++]
• Knowledge of formal languages, grammars and automata
• Knowledge of the structure and operation of a compiler
• Good ability to work in teams
• Flexibility, proactivity and independence in the approach to the research
The back-end development require the candidate to study and chose the accelerated hardware (with GPU, Graphics core, DSP, FPGA, etc..) to be used as testbench. Some of the available architectures are here listed:
• PULP [Cluster di CPU] http://www.pulp-platform.org/
• Xilinx Zynq [CPU+GPU+FPGA] https://www.xilinx.com/products/silicon-devices/soc.html
• STMicroElettronics STCOMET [CPU+DSP] http://www.st.com/
• Nvidia Jetson TX1 [GPU+CPU] http://www.nvidia.com/object/jetson-tx1-dev-kit.html
During the thesis work the candidate will use LLVM APIs and the LLVM intermediate representation.
Deadline 31/12/2017 PROPONI LA TUA CANDIDATURA