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Debugging Techniques and Tools for System-In-Package FPGA’s

Parole chiave DEBUG TOOLS DEVELOPMENT, EMBEDDED SYSTEMS, FPGA-BASED DESIGN, SYSTEM-IN-PACKAGE (SIP), VHDL

Riferimenti PAOLO ERNESTO PRINETTO

Riferimenti esterni Gianluca ROASCIO (CINI Cybersecurity National Laboratory)
Nicolò MAUNERO (CINI Cybersecurity National Laboratory)
Antonio VARRIALE (Blu5 Labs Ltd)

Gruppi di ricerca GR-21 - TESTGROUP - TESTGROUP

Tipo tesi MASTER THESIS

Descrizione In the integration system domain, SiP (System-In-Package) have received a consistent trend in the last decades. It consists in enclosing multiple dice, often coming from different companies, into a single chip carrier package through vertical stacking. This technique offers a valid alternative to heavy custom System-on-Chip (SoC) design and also overcomes the problem of connecting different integrated circuits (IC) onto boards. However, when packaging different circuits, isolation is lost and debugging of single components inside the SiP becomes an issue. The thesis work is about finding a debug solution for an FPGA packaged into a chip by Blu5™ called SEcube™, an embedded system with dedicate security and cryptography engine.

Note The thesis activities will be carried out in collaboration with:
- Blu5 Labs Ltd (Malta)
- CINI Cybersecurity National Laboratory


Scadenza validita proposta 22/05/2020      PROPONI LA TUA CANDIDATURA




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