Scoreboard Generic Library for an UVM Verification Environment
Reference persons EDGAR ERNESTO SANCHEZ SANCHEZ
External reference persons Annachiara Ruospo, Ph.D student
Research Groups DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Description UVM is a widespread and well-known verification methodology for System-on-Chip (SoC) functional verification. It helps the designers to find more bugs earlier in the design process. The UVM environment is made of many basic blocks, each with a specific task. One of the most complex is the Scoreboard: it is in charge of checking the correct functionality of the device under test (DUT). The thesis focuses on this module and consists on the development and test of a generic library for allowing a greater module portability.
This thesis is developed in cooperation with the Infineon PSN group in Padova; eventually, it would be possible to perform the thesis in the company and receive a cost refund during the thesis period.
Required skills C, Verilog, SystemVerilog
Deadline 10/03/2021 PROPONI LA TUA CANDIDATURA