Complementing the UVM Verification Framework with Formal Techniques
Reference persons EDGAR ERNESTO SANCHEZ SANCHEZ
External reference persons Annachiara Ruospo, Ph.D student
Research Groups DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Description The Universal Verification Methodology (UVM) is a standardised methodology for the verification of System-on-Chips (SoCs). The main intent of the thesis is to investigate the integration of formal techniques to speed-up the verification phase. The standard UVM verification environment should be supported by formal strategies to cover very well defined modules and to improve the whole process. The device under test (DUT) is an open-source RISC-V processor core.
This thesis is developed in cooperation with the Infineon PSN group in Padova; eventually, it would be possible to perform the thesis in the company and receive a cost refund during the thesis period.
Required skills C, Verilog, SystemVerilog
Deadline 10/03/2021 PROPONI LA TUA CANDIDATURA