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  KEYWORD

Automated Synthesis of Vulnerable RISC-V based Architectures

Parole chiave AUTOMATED SYNTHESIS, CAPTURE-THE-FLAG COMPETITIONS, COMPUTER ARCHITECTURES, CYBER CHALLENGES, CYBERRANGES, EDA ENVIRONMENTS, GAMIFICATION, GAMING, HARDWARE SECURITY, RISC-V, SECURITY, WHITE TEAMING

Riferimenti PAOLO ERNESTO PRINETTO

Riferimenti esterni Gianluca ROASCIO (CINI Cybersecurity National Laboratory)
Nicolò MAUNERO (CINI Cybersecurity National Laboratory)
Gaspare FERRARO (CINI Cybersecurity National Laboratory)
Zainalabedin NAVABI (Faculty of Engineering of the University of Tehran)
Antonio VARRIALE (Blu5 Labs, Malta)

Gruppi di ricerca GR-21 - TESTGROUP - TESTGROUP

Tipo tesi MASTER THESIS

Descrizione Training in hardware security more and more exploits gamification as a key asset to attract and increase students’ attention. Typical gaming-based approaches include Capture-the-Flag (CtF) challenges.

Microprocessors proved to play a key role in preparing nice challenges, since they can easily incorporate a huge variety of different vulnerabilities. At the same time, in order to minimize the efforts of the attendees in learning the processor architecture, it is strongly recommended that most of the hardware challenges proposed in a given training or in a competition exploit a same processor architecture. Moreover, such an architecture should preferably be a proper subset of some well-known computer architectures, such as, for instance the Risc-V one.

As the number of required hardware-based challenges increases, the task of preparing new stimulating scenarios becomes harder and harder. To make it easier, the availability of tools and environments capable of easily synthesizing new challenges is warmly envisaged.

In order to fulfil the above mentioned requirements, we decide to first design SAYAC, a Risc-V based simple processor and then to develop a tool that allow to simply and automatically generate custom versions of SAYAC, specifying, for each version, a specific set of artificially introduced vulnerabilities.

The purpose of the thesis is to join the design team set up to develop the Automated synthesis tool for the SAYAC processor. In particular, the tool will get in input the requirements expressed by the White Team and, starting from the SAYAC basic architecture, it will generates a Custom SAYAC RT-level description. Proper documentation is generated as-well, in order to support the White Team in preparing the challenge Write-up.

The thesis activities will be carried out in collaboration with researchers of:
- CINI Cybersecurity National Laboratory (https://cybersecnatlab.it)
- Faculty of Engineering of the University of Tehran
- Blu5® Labs Ltd (Malta)

Note The thesis activities will be carried out in collaboration with researchers of:
- CINI Cybersecurity National Laboratory (https://cybersecnatlab.it)
- Faculty of Engineering of the University of Tehran
- Blu5® Labs Ltd (Malta)

The topic is so huge that several students can be involved in the activities.


Scadenza validita proposta 31/12/2022      PROPONI LA TUA CANDIDATURA




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