| KEYWORD |
Area Engineering
Delay and sequence control in P4 switches
keywords PROGRAMMABLE DATA PLANES, P4
Reference persons ANDREA BIANCO, PAOLO GIACCONE
Research Groups Telecommunication Networks Group
Thesis type EXPERIMENTAL / DEVELOPMENT
Description :Data centers leverage multipath routing and cloud applications suffer from out-of-sequence messages.
The main idea of the thesis is to exploit the network and the internal processing pipeline as virtual buffers to recirculate the traffic and control the delay and the sequence of packets.
The network application will be developed in P4 language and the implementation will be based on the 2 high-performance P4 switches with 32 ports running at 100 Gbps in Politecnico laboratories.
Aim of the thesis will be to investigate how to use a programmable data plane to emulate a network.
Required skills Linux
Programming (excellent)
Network protocols and algorithms
Deadline 19/01/2025
PROPONI LA TUA CANDIDATURA