Optimization algorithms for test time minimization in board testers
Gruppi di ricerca GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Descrizione Testing of Printed Circuit Boards (PCBs) is normally done by equipment including 4 to 8 probes quickly moving from one test point to another and applying/sensing current and voltages. The sequence of movements of probes determines the time required by the test, which strongly affects its cost. Hence, identifying a minimal duration sequence of movements is crucial.
The thesis aims at further minimizing the sequence of movements of the probes in real PCB testers produced by SPEA (www.spea.com).
A prototypical tool has been already developed by Politecnico, but ideas exist for further improving its performance.
The thesis shall be performed in Politecnico's labs, in close cooperation with SPEA technicians, that will then validate the developed algorithms on the real testing machines.
Conoscenze richieste Good programming skills (in particular, C and C++).
Scadenza validita proposta 21/10/2019 PROPONI LA TUA CANDIDATURA