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Test program generation targeting delay faults for advanced automotive systems



Descrizione Electronic systems are increasingly used in application areas where safety is a major concern (e.g., automotive, biomedical, aerospace). In order to guarantee a sufficient level of reliability, mature technologies were adopted, thus mainly trading off reliability with performance. In fact, the strict target reliability figures required by certain standards (e.g., ISO 26262 for automotive) can hardly be achieved with the devices manufactured with some of the most advanced current semiconductor technologies. More recently, some new application areas, e.g., the Advanced Driver Assistance Systems (ADAS), which are quickly being introduced in new cars require very high computational throughput to process in real time the huge volume of data coming from on-board cameras, radars, lidars, etc. This situation becomes even more critical when considering electronic systems for autonomous and semi-autonomous vehicles. Very complex and high performance devices are used for these applications, resorting to leading edge semiconductor technologies, whose reduced maturity severely limits their reliability. To face this scenario two actions are becoming mandatory and are currently pursued by companies
Improving the quality of the test performed at the end of manufacturing, to avoid the risk that faulty components are mounted on the systems used on-board the vehicles
performing in-field test of the most critical components, thus detecting the occurrence of faults before they provoke serious failures.
In all the above cases, suitable test stimuli are required, targeting the most likely faults inside the device. Currently, most of these stimuli are based on carefully written programs executed by the CPU core which typically exists on-board the device. Until now, these programs are written targeting the usual stuck-at fault model. Given the increasingly advanced semiconductor technology used for manufacturing, it is likely that soon the importance of delay faults will increase. Hence, new techniques for developing suitable test programs targeting delay fault models are required.
The work proposed for the thesis consists in the development of such techniques and in their evaluation on some test cases corresponding to processor cores representative of the class used in most automotive Systems on Chip (e.g. OpenRISC 1200, or RISC V), resorting to state-of-the art EDA tools, such as Z01X by Synopsys.

Conoscenze richieste This work requires some basic knowledge about VHDL or Verilog, and about the architecture of a processor-based system.

Note The work will be performed in strict cooperation with STMicroelectronics.

Scadenza validita proposta 13/11/2019      PROPONI LA TUA CANDIDATURA

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