Evaluation of Defect-oriented Functional Testing techniques
Tesi esterna in azienda
Riferimenti MATTEO SONZA REORDA
Riferimenti esterni Michelangelo Grosso (STMicroelectronics)
Gruppi di ricerca GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Descrizione Today’s mixed-signal ASICs (circuits which integrate digital and analog subsystems) usually undergo a series of test steps at the end of manufacturing. First, digital parts are tested by means of scan patterns; then, analog circuits are verified using functional techniques, which require programming of logic devices and waveform stimulation of terminals. Providing a test coverage value for the logic at the interface between digital and analog parts is not straightforward, because scan chains cannot access it. This thesis aims at evaluating the test coverage of defects in such area, by means of system-level simulation of manufacturing test sets, and, when needed, at enriching the test set.
The thesis will be performed in the STMicroelectronics lab within Politecnico di Torino.
Scadenza validita proposta 05/02/2020 PROPONI LA TUA CANDIDATURA