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Digital Verification

azienda Tesi esterna in azienda    


Parole chiave DIGITAL VERIFICATION, UVM

Riferimenti MAURIZIO MARTINA, GUIDO MASERA

Gruppi di ricerca VLSILAB (VLSI theory, design and applications)

Descrizione Digital Verification is the way to guarantee the best silicon quality before tape-out. It consists of acquiring a reasonable confidence that a circuit will function correctly, under the assumption that no manufacturing fault is present.
Taking in account also that the time to market itís a very important factor in productsí development, the target is to remove all possible design errors before proceeding to the expensive chip manufacturing.
Due to growing complexity itís coming more difficult to cover all scenarios and working conditions. Digital verification and UVM methodology are the state of art of tools that allow to generate and to measure the coverage of the device under test before tape-out in order to guarantee the correct behavior. Verification time is reduced thanks randomization and simulation parallelisms. Further all the possible scenarios are automatically generated and self-checked, also highlighting cases never taken in account before to be analyzed.

Digital verification thesis proposal

1) Digital Verification trend in semiconductor industries
Digital Verification is the way to guarantee the best silicon quality before tape-out. It consists of acquiring a reasonable confidence that a circuit will function correctly, under the assumption that no manufacturing fault is present.
Taking in account also that the time to market itís a very important factor in productsí development, the target is to remove all possible design errors before proceeding to the expensive chip manufacturing.
Due to growing complexity itís coming more difficult to cover all scenarios and working conditions. Digital verification and UVM methodology are the state of art of tools that allow to generate and to measure the coverage of the device under test before tape-out in order to guarantee the correct behavior. Verification time is reduced thanks randomization and simulation parallelisms. Further all the possible scenarios are automatically generated and self-checked, also highlighting cases never taken in account before to be analyzed.

2) Thesis environment
The thesis will be in inside STMicroelectronics in HDD market products. The student will have the opportunity to be inside a design team in which the Digital Verification is an important part of product development

3) Activities and goals
SPI custom protocol coverage is one the major point to be developed in device.
The activities will be:
- to Learn building and using a digital verification environment
--> Compile and elaborate a RTL design
--> Use Cadence tools (xrun and xcelium) to launch the simulation and customized it
--> Create a system Verilog testbench

- to Learn System Verilog language and UVM methodology
--> Create a SPI UVM Verification IP
--> Create an UVM Register Map
--> Create a random stimuli test suite
--> Create verification object to monitor coverage:
--|--> Covergroups
--|--> Assertions
--> Learn to use
--|--> Assertion Browser
--|--> UVM Register Viewer
--|--> Metric Analysis Tool
--> Launch and monitor random test suites through Cadence VManager tool
--|--> to Learn to use the tool
--|--> Write a Verification Plan for the SPI and to collect coverage

- to Build an environment to create automatically a UVM Register Map

With at disposal all above instruments described, the student will stimuli randomly the device under test, monitor and analyze the coverage with the final target is to reach highest Code and Functional Coverage. The DUT will includes SPI and Register Map.

4) Tutoring
The student will be instructed by a senior verification design engineer who will provide all the necessary support for learning verification language, methodology and tools and will be a monitor on the thesis activity.


Scadenza validita proposta 15/10/2020      PROPONI LA TUA CANDIDATURA




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