| KEYWORD |
Area Architecture
High-performance software programming for reconfigurable network systems
keywords ARM BASED SYSTEMS, COMPANY, EMBEDDED SOFTWARE, EMBEDDED SYSTEM, OPERATING SYSTEMS, SOFTWARE
Reference persons CORRADO DE SIO, LUCA STERPONE
External reference persons LINKS Foundation contacts:
Alberto Scionti
Paolo Savio
Research Groups ASAC Lab - Aerospace, Safety, and Computing Lab, DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Thesis type COLLABORATION WITH A COMPANY
Description High-speed, low-latency networks are becoming a fundamental building block in many application contexts. For instance, in modern datacenters, high-speed, low-latency networks are required to better serving large AI models and big-data applications. FPGAs evolved in the past years to include more and more functionalities, like hardened processors and network building blocks. As such, modern FPGAs can be used to implement custom high-speed network interfaces (NICs).
The purpose of this thesis is the development of efficient low-level programs (firmware) running on top of ARM bare-metal processor cores (i.e., cores that are not under the direct control of the operating system). These processor cores will work in tandem with standard (application) cores (which run a Linux OS) to provide acceleration for both network packet routing/processing and the user application. To achieve this, the candidate will leverage dedicated software libraries (e.g., libmetal, OpenAMP) aimed at simplifying programming of heterogeneous systems. Validation experiments will be done at LINKS Foundation where a cluster of 6 FPGA boards is available.
Required skills Required Knowledge
- Programming Language ( C/C++ )
- Linux OS, and base of OS Programming
Notes This thesis is developed in collaboration with Links Foundation
Deadline 08/01/2026
PROPONI LA TUA CANDIDATURA