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Mapping an embedded Video application on FPGA using Berkeley's Rocket Chip RISC V platform

estero Tesi all'estero



Riferimenti esterni Prof. Mounir BENABDENBI (TIMA Laboratory, Grenoble)
Prof. Michele PORTOLAN (TIMA Laboratory, Grenoble)

Gruppi di ricerca TESTGROUP - TESTGROUP


Descrizione The RISC-V architecture is an open source instruction set architecture (ISA), developed at University of California Berkley (UCB) to serve as an open standard for both academia and industry. RISC V based processors are gaining more and more popularity in the semiconductor industry (Nvidia, Greenwaves, ...) and make them good challengers to ARM microprocessors. UCB is also proposing Rocket Chip, a system on chip generator embedding RISC V processor cores. The Rocket Chip framework allows generating tunable hardware and software binaries.
In this context, the proposed internship goal is to select a modern video application and map it on a Xilinx FPGA using the Rocket Chip toolset.
This project is a part of an educational project aiming at teaching the tight relationship between hardware and software using RISC V processors.
A preliminary work has been done to understand and use the Rocket Chip platform (software and hardware components). First labs have been defined but they need to be improved to target a realistic application running on a modern FPGA.
Depending on the work progress, the platform may also be tuned to allow multi-tasking applications running on a multi-core SoC: neuromorphic and/or machine learning applications
Internship tasks:
Become familiar with the RISCV processor and Rocket Chip ecosystem
Improve the existing labs in order to run small educational programs on different
hardware versions
Map the system design, including the processor, a memory, a bus interconnect, ...
on a high end Xilinx FPGA
Validate the architecture running on the FPGA, first with simple applications and
then with a realistic video application, probably a convolutional neural network
Write documentation and labs/tutorials for students
Study how to design and run a multi-tasking application on a multi-core SoC

Conoscenze richieste Very good knowledge of VHDL/Verilog, CPU based system architecture, embedded system knowledge (HW and SW), FPGA programming.
Bonus skills: Experience with RISC V architecture, System Verilog and Chisel language is greatly appreciated.

Note Possibility to spend 5 months at the University of Grenoble (TIMA Laboratory)

Scadenza validita proposta 29/01/2020      PROPONI LA TUA CANDIDATURA

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