Servizi per la didattica
PORTALE DELLA DIDATTICA

Digital systems electronics

01OIHNX, 01OIHOD

A.A. 2018/19

Course Language

Inglese

Course degree

1st degree and Bachelor-level of the Bologna process in Electronic Engineering - Torino
1st degree and Bachelor-level of the Bologna process in Physical Engineering - Torino

Borrow

02OIHLP

Course structure
Teaching Hours
Lezioni 47
Esercitazioni in laboratorio 33
Teachers
Teacher Status SSD h.Les h.Ex h.Lab h.Tut Years teaching
Masera Guido Professore Ordinario ING-INF/01 47 0 66 0 8
Teaching assistant
Espandi

Context
SSD CFU Activities Area context
ING-INF/01
ING-INF/01
ING-INF/01
5
2
1
B - Caratterizzanti
E - Per prova finale e conoscenza della lingua straniera
F - Altre (art. 10, comma 1, lettera f)
Ingegneria elettronica
Per la prova finale
AbilitÓ informatiche e telematiche
2018/19
The course is mandatory for the BSc-level programme in Electrical Engineering and will be offered in the second period of the third year. It is focussed on the basics of Digital Electronics, considering and studying the different aspects of digital design. A lot of methodologies related to basic digital circuits up to complex processing systems will be shown and used. The knowledges and the abilities developed in this module will constitue the solid bases of the following corses where digital systems will be considered in more details.
The course is mandatory for the BSc-level programme in Electrical Engineering and will be offered in the second period of the third year. It is focussed on the basics of Digital Electronics, considering and studying the different aspects of digital design. A lot of methodologies related to basic digital circuits up to complex processing systems will be shown and used. The knowledges and the abilities developed in this module will constitue the solid bases of the following corses where digital systems will be considered in more details.
- Knowledge of basic combinatorial circuits and their synthesis tools; - Knowledge of sequential circuits and their synthesis tools; - Knowledge and ability in the use of a Hardware Description Language such as VHDL: description and syntesis of digital blocks. - Knlowledge of complex programming digital circuits (FPGAs); - Knowledge of memory structures and architectures, and their use in processing systems. - Knowledge of microcontrollers architectures and applications.
- Knowledge of basic combinatorial circuits and their synthesis tools; - Knowledge of sequential circuits and their synthesis tools; - Knowledge and ability in the use of a Hardware Description Language such as VHDL: description and syntesis of digital blocks. - Knlowledge of complex programming digital circuits (FPGAs); - Knowledge of memory structures and architectures, and their use in processing systems. - Knowledge of microcontrollers architectures and applications.
Boole's Algebra; elementary combinatorial and sequential digital gates; FSM concept, basic processor architecture and its programming paradigm (assembler language)
Boole's Algebra; elementary combinatorial and sequential digital gates; FSM concept, basic processor architecture and its programming paradigm (assembler language)
- Combinatorial circuits: synthesis techinques for basic and arithmetic circuits (2 CFU) - Sequential circuits: elementary FSMs and complex control architectures (ASM charts) (2 CFU) - Hardware Description Languages (VHDL): statements, data structures and coding techniques for hardware description and modelling (2 CFU); - Memories: circuits, architectures and applications (1 CFU); - Microcontrollers: internal architecture, programming model and use; peripheral units (3 CFU);
- Combinatorial circuits: synthesis techinques for basic and arithmetic circuits (2 CFU) - Sequential circuits: elementary FSMs and complex control architectures (ASM charts) (2 CFU) - Hardware Description Languages (VHDL): statements, data structures and coding techniques for hardware description and modelling (2 CFU); - Memories: circuits, architectures and applications (1 CFU); - Microcontrollers: internal architecture, programming model and use; peripheral units (3 CFU);
Practice classes will focus on small digital designs (personal calculator required). Lab sessions consist in the development, synthesis and implementation of digital designs, described using VHDL, and microcontrollers, possibly integrated into FPGAs . Evaluation boards will be available to test the designs. 7 or 8 lab sessions will be provided by groups of 2 or 3 students. Homeworks are required to prepare the lab sessions. A report is required for the lab sessions and will be considered in the final grade.
Practice classes will focus on small digital designs (personal calculator required). Lab sessions consist in the development, synthesis and implementation of digital designs, described using VHDL, and microcontrollers, possibly integrated into FPGAs . Evaluation boards will be available to test the designs. 7 or 8 lab sessions will be provided by groups of 2 or 3 students. Homeworks are required to prepare the lab sessions. A report is required for the lab sessions and will be considered in the final grade.
The learning material used for the lessons is made available through the course website. Notes provided by the professor. Reference books: "Fundamentals of Digital Logic with VHDL Design (Third Edition)" di Stephen Brown e Zvonko Vranesic , Mc Graw Hill 'Microcontroller Theory and Applications:HC12 and S12' (Second Edition), D. Pack, S. Barrett, Pearson, Prentice Hall.
The learning material used for the lessons is made available through the course website. Notes provided by the professor. Reference books: "Fundamentals of Digital Logic with VHDL Design (Third Edition)" di Stephen Brown e Zvonko Vranesic , Mc Graw Hill 'Microcontroller Theory and Applications:HC12 and S12' (Second Edition), D. Pack, S. Barrett, Pearson, Prentice Hall.
ModalitÓ di esame: prova scritta; prova orale obbligatoria; progetto di gruppo;
The written test includes three open answer questions and one design problem. The available time is 2 hours. The questions cover all course topics and they intend to verify the acquired knowledge and capabilities. The design problem requires to understand the initial specifications, to develop a detailed datapath architecture, to properly model the control unit, and to describe one or multiple elements by means of VHDL. No books and notes are admitted. Normally, the same weight is given to each question. However, the weight of questions that achieved a very low average mark may be slightly reduced. A mark at least equal to 18/30 is required to pass to the oral exam, which concerns both the subjects already covered in the written test and the discussion of the submitted projects. Normally, two questions are asked and one of them is about laboratory projects. The evaluation of laboratory projects is based on: - completeness, - adopted methodology - obtained results. The final grade is a weighted average of the written and oral exams (weighted 0.8) and lab reports (weighted 0.2).
Exam: written test; compulsory oral exam; group project;
The written test includes three open answer questions and one design problem. The available time is 2 hours. The questions cover all course topics and they intend to verify the acquired knowledge and capabilities. The design problem requires to understand the initial specifications, to develop a detailed datapath architecture, to properly model the control unit, and to describe one or multiple elements by means of VHDL. No books and notes are admitted. Normally, the same weight is given to each question. However, the weight of questions that achieved a very low average mark may be slightly reduced. A mark at least equal to 18/30 is required to pass to the oral exam, which concerns both the subjects already covered in the written test and the discussion of the submitted projects. Normally, two questions are asked and one of them is about laboratory projects. The evaluation of laboratory projects is based on: - completeness, - adopted methodology - obtained results. The final grade is a weighted average of the written and oral exams (weighted 0.8) and lab reports (weighted 0.2).


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