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Development of a Soft Error tolerant Parallel Hash Table on FPGAs for safety critical applications

keywords FAULT TOLERANCE, FPGA, FPGA ACCELERATION

Reference persons LUCA STERPONE

Research Groups DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD

Thesis type RESEARCH / EXPERIMENTAL

Description A key component in Artificial Intelligence and Machine Learning applications is the fast execution of quicl search and retrieval of data. Hash tables are a fundamental data structure to perform these operation efficiently. In safety critical applications such as automotive or aerospace, it is not sufficient to have a performant architecture but it is also necessary to guarantee a given level of robustness and protection versus soft errors. In the present thesis, the student will explore, study and development a new architecture for implementing parallel and fault tolerant hash table for SRAM-based FPGAs for aerospace applications. The thesis will be performed in collaboration with the European Space Agency (ESA) and in cooperation with AMD/Xilinx.

Required skills Design of Circuits and Systems in VHDL or Verilog.
Preliminary basic knowledge of FPGA architectures.


Deadline 30/11/2022      PROPONI LA TUA CANDIDATURA