TESI AZIENDA
5G Physical Layer on USRP Platforms
GAUDINO ROBERTO
Optical Communication group (OPTCOM)
|
Acceleration of software applications via High-Level Synthesis for FPGAs
LAVAGNO LUCIANO
LAZARESCU MIHAI TEODOR
microelettronica
|
Adaptable Dynamically Reconfigurable Hardware for Space Mission Rovers
STERPONE LUCA
ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
An Open-source Self Reconfigurable Architecture for Aerospace Applications
STERPONE LUCA
GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Design and development of a Muon detector
STERPONE LUCA
DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Design and development of a digital real-time co-simulation infrastructure for scalable power system transition scenarios
BARBIERATO LUCA
PATTI EDOARDO
EDA Group
Energy Center Lab
|
Design of a FPGA-based MPEG compression algorithm for UAV payload
DI CARLO STEFANO
PRINETTO PAOLO ERNESTO
TESTGROUP - TESTGROUP
|
Design of a FPGA-based OCR algorithm for UAV payload control
DI CARLO STEFANO
PRINETTO PAOLO ERNESTO
TESTGROUP - TESTGROUP
|
Design of a FPGA-based TPM Security Device
DI CARLO STEFANO
PRINETTO PAOLO ERNESTO
TESTGROUP - TESTGROUP
|
Design of a FPGA-based processor for UAV payload control
DI CARLO STEFANO
PRINETTO PAOLO ERNESTO
TESTGROUP - TESTGROUP
|
Design of high performance memory systems for Datacenter Embedded Systems
STERPONE LUCA
DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
|
TESI ALL'ESTERO
Development of a FPGA radiation tolerant microcontroller interface for LHC facility
STERPONE LUCA
GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Development of a Soft Error tolerant Parallel Hash Table on FPGAs for safety critical applications
STERPONE LUCA
DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
TESI ALL'ESTERO
Development of a methodology using software defined radios for magnetic measurement setups
GRAZIANO MARIAGRAZIA
RIENTE FABRIZIO
VLSILAB (VLSI theory, design and applications)
|
Development of an FPGA prototype of a novel fully digital D/A converter for System-on-Chips in nanoscale CMOS
CASU MARIO ROBERTO
CROVETTI PAOLO STEFANO
VLSILAB (VLSI theory, design and applications)
|
Development of an innovative Hybrid HW/SW Architecture
DI CARLO STEFANO
PRINETTO PAOLO ERNESTO
TESTGROUP - TESTGROUP
|
EXOMARS test bench development
VIOLANTE MASSIMO
ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Enhancing Qubit Control and Readout: FPGA RTL Adaptation on the QICK Platform for Superconducting Quantum Experiments
GRAZIANO MARIAGRAZIA
RIENTE FABRIZIO
TURVANI GIOVANNA
ZAMBONI MAURIZIO
VLSILAB (VLSI theory, design and applications)
|
Enhancing dependability in FPGA-based systems for future space exploration missions
DI CARLO STEFANO
PRINETTO PAOLO ERNESTO
TESTGROUP - TESTGROUP
|
Evaluation methods for the robustness of a radiation tolerant RISC-V processor for deep space applications
STERPONE LUCA
DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
FPGA IP development for modular architectures on the VirtLAB board
RUO ROCH MASSIMO
VLSILAB (VLSI theory, design and applications)
|
FPGA-based HW Design for Digital Signal Processing for Advanced Audio Beamforming
RIENTE FABRIZIO
TURVANI GIOVANNA
ZAMBONI MAURIZIO
VLSILAB (VLSI theory, design and applications)
|
FPGA-based accelerators for future Mars exploration missions
DI CARLO STEFANO
PRINETTO PAOLO ERNESTO
TESTGROUP - TESTGROUP
|
Floor planning for FPGAs
LAVAGNO LUCIANO
microelettronica
|
Hardware-based Machine Learning for Event-Based sEMG-based Gesture Recognition
DEMARCHI DANILO
MOTTO ROS PAOLO
MiNES (Micro&Nano Electronic Systems)
|
High-performance network systems on reconfigurable hardware (FPGA)
DE SIO CORRADO
STERPONE LUCA
ASAC Lab - Aerospace, Safety, and Computing Lab
DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Improve robustness of FPGA dataflow accelerators for Convolutional Neural Networks
PASSERONE CLAUDIO
|
Lightweight AI inference on Embedded Systems
STERPONE LUCA
DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
|
Methods for the dependability evaluation of FPGA with dynamic reconfiguration
STERPONE LUCA
ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
TESI AZIENDA
Microprocessor-based Self Test for on-line testing of airplane electronic system
STERPONE LUCA
ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
TESI AZIENDA
Microprocessor-based Self Test for on-line testing of airplane electronic system
STERPONE LUCA
DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
|
TESI AZIENDA
Microprocessor-based Selft Test for on-line testing of airplane electronic system
STERPONE LUCA
ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Microwave Technology for Brain Imaging and Monitoring
CASU MARIO ROBERTO
VIPIANA FRANCESCA
Applied Electromagnetics
VLSI THEORY, DESIGN AND APPLICATIONS (VLSILAB)
|
TESI AZIENDA
Noise analysis in FPGA for time and frequency metrology
COSTANZO GIOVANNI ANTONIO
|
On the implementation and reliability analysis of the Embedded Soft-processor on Reconfigurable Devices
AZIMI SARAH
DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Resilient FPGA implementations of Deep Neural Networks
CASU MARIO ROBERTO
LAVAGNO LUCIANO
LAZARESCU MIHAI TEODOR
VLSILAB (VLSI theory, design and applications)
|
Speech Rate Recognition @Centro Ricerche e Innovazione Tecnologica RAI
PRINETTO PAOLO ERNESTO
TESTGROUP - TESTGROUP
|
Study and Development Quantum Systems integrated with Field Programmable Gate Arrays (FPGAs)
STERPONE LUCA
DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
|
Study and Development Quantum Systems integrated with Field Programmable Gate Arrays (FPGAs)
STERPONE LUCA
DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
|
Study and development of Reliable RISC-V Architectures for space applications
DE SIO CORRADO
STERPONE LUCA
ASAC Lab - Aerospace, Safety, and Computing Lab
DAUIN - GR-05 - ELECTRONIC CAD and RELIABILITY GROUP - CAD
|
Study and development of a satellite-oriented quantum communication system on FPGAs
STERPONE LUCA
DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
|
Study and development of enhanced SRAM configuration memory for the new generation of reconfigurable SoC
SONZA REORDA MATTEO
STERPONE LUCA
ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Study and development of fault tolerance mitigation methods for TPU architectures
STERPONE LUCA
DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Study and development of new TPU architectures for High Performance Computing applications
STERPONE LUCA
DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
|
Study and development of new computer architecture for space applications based on RISC-V processor
STERPONE LUCA
DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
|