Design of high performance memory systems for Datacenter Embedded Systems
Reference persons LUCA STERPONE
Research Groups DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
Description The main goal of this thesis is to design an efficient architecture for access to the memory system of datacenter FPGA using High Level Synthesis accelerator design. A specific set of memory bound applications will be used to evaluate the available off-chip memory bandwidgth. The design will be tuned according to the following steps: number of concurrent memory access, the data size of each memory port, the maximum burst lenght of each port and the size and time of the consecutive data access.
The thesis has an high research orientation and it is performed in cooperation with the Xilinx company.
Required skills Computer Architecture, Operative Systems
Notes High Level Synthesis, Accelerators
Deadline 01/11/2023 PROPONI LA TUA CANDIDATURA