FPGA IP development for modular architectures on the VirtLAB board
Reference persons MASSIMO RUO ROCH
Research Groups VLSILAB (VLSI theory, design and applications)
Description Thesis target is the development of functional blocks (IP's) based on Altera Cyclone 10 LP FPGA's, used to build complex objects hosted on the FPGA's of the VirtLAB board.
The modules must be compatible with the existing hardware, and have a standard Avalon interface.
These block can range from simple interfaces (HyperBus master, QSPI master/slave), up to complex processing blocks (AI accelerators, DSP, etc.)
Deadline 01/03/2024 PROPONI LA TUA CANDIDATURA