RESEARCH GROUPS

Area Architecture

Area Engineering

DEPARTMENTS

Improve robustness of FPGA dataflow accelerators for Convolutional Neural Networks

keywords CNNS, FPGA, HLS, HW, ROBUSTNESS, TRAINING

Reference persons CLAUDIO PASSERONE

External reference persons Pierpaolo Morì

Thesis type RESEARCH

Description The aim of this thesis is to demonstrate the effectiveness of Fault Aware Training (FAT) on dataflow FPGA accelerators for CNNs. The work will be organized in two main milestones:
• Training a CNN model modeling HW soft-errors at training time. 
• Evaluate the effectiveness of the trained model on a faulty FPGA accelerator.

See also  thesisproposal_fat.pdf 

Required skills Python, FPGA design

Deadline 26/11/2023      PROPONI LA TUA CANDIDATURA