| KEYWORD |
Cross-layer fault modeling and online fault detection and diagnosis for NoC
Parole chiave DEPENDABLE SYSTEM DESIGN, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, FAULT DETECTION, FAULT MODELING, NETWORK-ON-CHIP
Riferimenti STEFANO DI CARLO, PAOLO ERNESTO PRINETTO
Riferimenti esterni INDACO Marco (PhD Candidate)
GAMBARDELLA Giulio (PhD Student)
Gruppi di ricerca TESTGROUP - TESTGROUP
Tipo tesi EXPERIMENTAL
Descrizione Motivation:
Network-on-Chips are emerging as a new communication infrastructure to supersede the traditional bus structures. Therefore, reliability and fault tolerance are challenges in research. The combination and interaction of techniques on different layers, targeting multiple fault mechanisms, will led to an innovative reliable solution for NoCs.
Goals:
The thesis aims at setting-up an online fault diagnosis and localization, using a peculiar cross-layer fault modeling approach. Appropriate functional fault models should be defined and used for online monitoring of the multi-layer Network-on-Chip.
Learning Outcomes:
During this thesis the candidate will learn how to set-up fault models, and gain skill on how to use that during a system design
Conoscenze richieste Programming Languages: SPICE, VHDL, C
Digital System design methodologies
Note The thesis will be developed within the framework of a joint research project between the Testgroup of Politecnico di Torino and the Inst. für Technische Informatik, Universität Stuttgart (Germany), prof. Hans-joachim Wunderlich.
Scadenza validita proposta 31/12/2012
PROPONI LA TUA CANDIDATURA