Design of optimized hardware modules for low-power ECC IP cores
Parole chiave BCH CODES, CORRECTING CODES, DIGITAL SYSTEM DESIGN, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, ECC, HIGH LEVEL SYNTHESIS TOOLS, IP CORES, LOW-POWER HARDWARE DESIGN, SYSTEM LEVEL DESIGN & TEST
Riferimenti esterni INDACO Marco (PhD Candidate)
Gruppi di ricerca TESTGROUP - TESTGROUP
Tipo tesi EXPERIMENTAL
Nowadays Error Correction Codes (ECCs) are widely adopted a fault-tolerance mechanism in several contexts (e.g., communication protocols, memory devices, etc.) to improve yield, reliability and endurance. To reach better performances an hardware implementation is usually preferred.
In particular, Bose-Chaudhuri-Hocquenghem (BCH) codes are a family of ECCs largely applied to modern Flash memories to significantly improve their endurance and reliability.
Generally, BCH code's system architecture is composed by two principal modules: encoder and decoder.
While computational resources required by encoder can be neglected, designing BCH decoder can be a crucial issue for the performance of overall system in terms of latency, area and power consumption.
In detail, a typical BCH decoder is made up by three modules: Syndrome machine, Berlekamp machine and Chien machine.
The goal of the thesis is to explore innovative solutions to design decoder architectures with emphasis on the critical issue of minimizing the power consumption of the decoder's modules (i.e, Syndrome machine, Berlekamp machine and Chien machine) in according with state-of-the-art methodologies for low power design.
The candidate will acquire a basic knowledge of the BCH codes, system level design methodology, skills on the system RTL description and gain a good experience about low-power design.
Note The thesis will be developed within the framework of a joint research project between the Testgroup of Politecnico di Torino and MPSoC group of UniversitÓ di Ferrara.
Number of required Students: 1 or 2
Scadenza validita proposta 31/12/2012 PROPONI LA TUA CANDIDATURA