| KEYWORD |
Design of Flash memory controller for hardware evaluation framework
Parole chiave DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, SYSTEM LEVEL DESIGN & TEST
Riferimenti STEFANO DI CARLO, PAOLO ERNESTO PRINETTO
Riferimenti esterni INDACO Marco (PhD Candidate), GALFANO Salvatore (PhD Candidate)
Gruppi di ricerca TESTGROUP - TESTGROUP
Tipo tesi EXPERIMENTAL AND SIMULATION
Descrizione Motivations:
Nowadays Flash Memories are pervasively used in many classes of computing systems. Many optimizations can be done at different levels of the overall memory architecture. Namely, a memory architecture is composed of several levels (from the bottom to the top): the Flash memory, its controller, the Memory Technology Device (MTD) or a more generic Device Driver, the File System (possibly a Flash-specific one, like YAFFS), and then Virtual File System and Applications.
Assessing the performances, in terms of a given architecture at different levels of the system is not such an easy operation. It is possible to do it by properly instrumenting the various levels of the system and emulating the Flash memory and its controller, however, trustworthiness of these results is limited due to device emulation.
To better and more precisely evaluate the system performance, an (adaptable) hardware prototype of the system is going to be developed. Such prototype will rely on a general purpose computer, an FPGA (to provide the memory controller) and a NAND Flash Memory chip.
Goals:
The goal of the thesis is to design a Flash memory controller for FPGA, to be used within a general purpose computing platform. First, architecture will have to be examined and possible design choice will have to be afforded. Second, synthesizable VHDL description of the controller will have to be produced.
Learning outcomes:
The candidate will acquire a basic knowledge of system level design methodology, skills on the system RTL description and operating systems.
Conoscenze richieste Programming Languages: C, VHDL
Digital System design methodologies, Computer Architecture
Note Number of required Students: 1 or 2
Scadenza validita proposta 15/03/2013
PROPONI LA TUA CANDIDATURA