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Keyword: FPGA ACCELERATION

5G Active Antenna profiling by using FPGA acceleration  LAVAGNO LUCIANO  High-Level Synthesis and FPGA acceleration
Design of a hardware module for online learning on Spiking Neural Networks, with partial reconfiguration on FPGA.  DI CARLO STEFANO  SAVINO ALESSANDRO  DAUIN - GR-24 - SMILIES - reSilient coMputer archItectures and LIfE Sci
Development of a Soft Error tolerant Parallel Hash Table on FPGAs for safety critical applications  STERPONE LUCA  DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Development of a tool for the optimization of Spiking Neural Networks (SNN) for the development of dedicated hardware accelerators on FPGA platform to apply in IoT and edge-computing environments.  DI CARLO STEFANO  SAVINO ALESSANDRO  DAUIN - GR-24 - SMILIES - reSilient coMputer archItectures and LIfE Sci
FPGA-based acceleration of Open Air Interface physical layer modules  LAVAGNO LUCIANO  High-Level Synthesis and FPGA acceleration
Food contamination monitoring via microwave imaging technology  CASU MARIO ROBERTO  SAVORANI FRANCESCO  VIPIANA FRANCESCA  Applied Electromagnetics  VLSI THEORY, DESIGN AND APPLICATIONS (VLSILAB)
Machine learning techniques for microwave brain stroke detection and classification  CASU MARIO ROBERTO  VIPIANA FRANCESCA  Applied Electromagnetics  VLSI THEORY, DESIGN AND APPLICATIONS (VLSILAB)
Machine learning techniques for microwave food contamination detection  CASU MARIO ROBERTO  VIPIANA FRANCESCA  Applied Electromagnetics  VLSI THEORY, DESIGN AND APPLICATIONS (VLSILAB)
Optimization of a hardware accelerator for Spiking Neural Networks for low power applications at the edge.  DI CARLO STEFANO  SAVINO ALESSANDRO  DAUIN - GR-24 - SMILIES - reSilient coMputer archItectures and LIfE Sci
Porting of a hardware accelerator for Spiking Neural Networks and its software driver on a Xilinx PynQ board for edge applications.  DI CARLO STEFANO  SAVINO ALESSANDRO  DAUIN - GR-24 - SMILIES - reSilient coMputer archItectures and LIfE Sci
Simultaneous Training and Hardware Optimization of Deep Neural Networks  CASU MARIO ROBERTO  VLSILAB (VLSI theory, design and applications)
Study and development of fault tolerance mitigation methods for TPU architectures  STERPONE LUCA  DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Study and development of new TPU architectures for High Performance Computing applications  STERPONE LUCA  DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Study and development of new computer architecture for space applications based on RISC-V processor  STERPONE LUCA  DAUIN - AEROSPACE AND SAFETY COMPUTING LAB


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