Resilient FPGA implementations of Deep Neural Networks
keywords DEEP NEURAL NETWORKS, ERROR TOLERANCE, FPGA, LOW POWER, SPACE APPLICATION
Reference persons MARIO ROBERTO CASU, LUCIANO LAVAGNO, MIHAI TEODOR LAZARESCU
Research Groups VLSILAB (VLSI theory, design and applications)
Description Deep Neural Networks (DNNs) are currently used mostly in application scenarios where a certain amount of imprecision in the computation is acceptable. This makes DNNs potentially resilient to hardware errors that can happen in different contexts, for example in space applications where ionizing radiations can result in bit flips in memory elements or in low-power applications where the use of very low voltages can cause timing errors. The resiliency can be obtained by a combination of DNN training techniques (aimed at improving the tolerance to errors of the DNN itself) and by hardware design techniques (aimed at improving the tolerance to errors of the logic circuits that implement the DNN). In SRAM-based FPGA, another potential source of error to consider in the picture is the bit flip of the FPGA configuration memory. The goal of the thesis is to study, design, implement, and test in FPGA a mix of training-time, design-time and run-time solutions to error tolerant DNNs. The thesis work is done in collaboration with AIKO (https://www.aikospace.com/).
Deadline 26/10/2023 PROPONI LA TUA CANDIDATURA