Study and development of new computer architecture for space applications based on RISC-V processor
Reference persons LUCA STERPONE
Research Groups DAUIN - AEROSPACE AND SAFETY COMPUTING LAB
Thesis type APPLIED RESEARCH
Description The thesis activity will focus on the design of a RISC-V computing architecture for aerospace. The architecture will be implemented on latest generation reconfigurable FPGA devices including Xilinx Ultrascale+. The thesis activity is carried out in collaboration with the European Space Agency (ESA) and with Microchip. During this thesis, it is possible to activate a visiting period in ESA. The thesis is supported by a scholarship.
Required skills good VHDL knowledge, basic Python experience and interest on embedded hardware systems design techniques.
Deadline 26/01/2024 PROPONI LA TUA CANDIDATURA